The antenna effect is an effect that can potentially cause yield and reliability problems during manufacturing of metal-oxide-semiconductor (MOS) integrated circuits. The substantial charge collected during processing can lead to possible damage to devices. Such in-process charging effects can be generated during plasma enhanced processing, such as high density plasma (HDP) and plasma enhanced chemical vapor deposition (PECVD) thin film depositions, and etching process during back end of line (BEOL).
In some cases, the plasma charging effect plays a critical role in silicon-oxide-nitride-oxide-silicon (SONOS) charge-trapping devices. In some flash memory devices, either PN diode protection or poly fuse protection is adopted. In some cases, convention complementary metal-oxide-semiconductor (CMOS) logic process use antenna rules (AR) to check an allowable ratio of metal gate to gate area. Once the checking result violate the AR, there are some ways to fix the violation, for example, changing routing layers to immediately connect a gate to the highest metal layers, adding a via near the gate to connect the gate to the highest layer, or adding a reverse diode that can be formed away from a transistor's source/drain, with an n+ implant in a p-substrate or with a p+ implant in an n-well.